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| author | Taniya Das <tdas@codeaurora.org> | 2018-06-23 17:19:26 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-07-07 02:46:22 +0300 |
| commit | 6c79d12e945e85556674a04cde13657a5d7943da (patch) | |
| tree | bc407ffc3267b7a81f2e2bc802c8c3e6d71114ea /Documentation/devicetree/bindings/clock | |
| parent | da172d2b6ba8c98101b9c18a986758662a91adbb (diff) | |
| download | linux-6c79d12e945e85556674a04cde13657a5d7943da.tar.xz | |
dt-bindings: clock: Introduce QCOM Display clock bindings
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,dispcc.txt | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt new file mode 100644 index 000000000000..d639e18d0b85 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt @@ -0,0 +1,19 @@ +Qualcomm Technologies, Inc. Display Clock Controller Binding +------------------------------------------------------------ + +Required properties : + +- compatible : shall contain "qcom,sdm845-dispcc" +- reg : shall contain base register location and length. +- #clock-cells : from common clock binding, shall contain 1. +- #reset-cells : from common reset binding, shall contain 1. +- #power-domain-cells : from generic power domain binding, shall contain 1. + +Example: + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0xaf00000 0x100000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; |