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| author | Heiko Stuebner <heiko@sntech.de> | 2015-11-04 15:25:16 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2015-11-19 07:53:35 +0300 |
| commit | 9def7ccfe8d5b84d382cff83553dd6db72f61a23 (patch) | |
| tree | 7061bbdb53cc2c09e20e82df005cc5944b9c6efa /Documentation/devicetree/bindings/arm | |
| parent | 8005c49d9aea74d382f474ce11afbbc7d7130bec (diff) | |
| download | linux-9def7ccfe8d5b84d382cff83553dd6db72f61a23.tar.xz | |
ARM: rockchip: add support smp for rk3036
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Xing Zheng <zhengxing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cpus.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87fef20..8fb074996caf 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -200,6 +200,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" |