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authorTao Zhang <quic_taozha@quicinc.com>2024-02-04 08:30:40 +0300
committerSuzuki K Poulose <suzuki.poulose@arm.com>2024-02-12 13:29:47 +0300
commit19bfaff3845727f354079a140f092336d97e5c1e (patch)
treee03d7244260bec61ed975a7706dafcde5356c12d /Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
parentdc6ce57e2aa0b10b0b78517245ea0ba47eed75b1 (diff)
downloadlinux-19bfaff3845727f354079a140f092336d97e5c1e.tar.xz
dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register
Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) for TPDM. It specifies the number of CMB MSR registers supported by the TDPM. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1707024641-22460-10-git-send-email-quic_taozha@quicinc.com
Diffstat (limited to 'Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml')
-rw-r--r--Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml10
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
index 2320b5445900..d0647ffaed71 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
@@ -69,6 +69,15 @@ properties:
minimum: 0
maximum: 32
+ qcom,cmb-msrs-num:
+ description:
+ Specifies the number of CMB MSR(mux select register) registers supported
+ by the monitor. If this property is not configured or set to 0, it means
+ this TPDM doesn't support CMB MSR.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 32
+
clocks:
maxItems: 1
@@ -123,6 +132,7 @@ examples:
reg = <0x06c29000 0x1000>;
qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";