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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2021-01-02 23:59:01 +0300
committerKevin Hilman <khilman@baylibre.com>2021-02-03 21:22:10 +0300
commit68f3a096d0f3552320635347de68a3bd7abd5d36 (patch)
tree9f74dd7fce68628edec37b7de7d8cc654ed655df /Documentation/devicetree/bindings/arm/amlogic
parent5d3f5d46de425ff0cbbc39faea0d7580c8afdb44 (diff)
downloadlinux-68f3a096d0f3552320635347de68a3bd7abd5d36.tar.xz
dt-bindings: Amlogic: add the documentation for the SECBUS2 registers
The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which contains registers for various IP blocks such as pin-controller bits for the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. The registers can be accessed directly when not running in "secure mode". When "secure mode" is enabled then these registers have to be accessed through secure monitor calls. So far these SoCs are always known to boot in "non-secure mode". Add a binding documentation using syscon (as these registers are shared across different IPs) for the SECBUS2 registers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210102205904.2691120-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'Documentation/devicetree/bindings/arm/amlogic')
-rw-r--r--Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml42
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diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
new file mode 100644
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+++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+description: |
+ The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which
+ contains registers for various IP blocks such as pin-controller bits for
+ the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits.
+ The registers can be accessed directly when not running in "secure mode".
+ When "secure mode" is enabled then these registers have to be accessed
+ through secure monitor calls.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - amlogic,meson8-secbus2
+ - amlogic,meson8b-secbus2
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ secbus2: system-controller@4000 {
+ compatible = "amlogic,meson8-secbus2", "syscon";
+ reg = <0x4000 0x2000>;
+ };