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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-06-12 19:36:37 +0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-07-17 16:36:01 +0400 |
| commit | 783c8f4c84451bc444e314a71b447239c6ef6fd9 (patch) | |
| tree | ccf8ed545ac850e06d3e781a99769bd0ea43c597 /Documentation/ABI/testing/sysfs-driver-tegra-fuse | |
| parent | 35874f3617b38e0c1f72163407c41d554a8f5939 (diff) | |
| download | linux-783c8f4c84451bc444e314a71b447239c6ef6fd9.tar.xz | |
soc/tegra: Add efuse driver for Tegra
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.
While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/ABI/testing/sysfs-driver-tegra-fuse')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-driver-tegra-fuse | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse new file mode 100644 index 000000000000..69f5af632657 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-tegra-fuse @@ -0,0 +1,11 @@ +What: /sys/devices/*/<our-device>/fuse +Date: February 2014 +Contact: Peter De Schrijver <pdeschrijver@nvidia.com> +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114 + and Tegra124 SoC's from NVIDIA. The efuses contain write once + data programmed at the factory. The data is layed out in 32bit + words in LSB first format. Each bit represents a single value + as decoded from the fuse registers. Bits order/assignment + exactly matches the HW registers, including any unused bits. +Users: any user space application which wants to read the efuses on + Tegra SoC's |