diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2026-01-28 23:50:33 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-02-06 22:53:29 +0300 |
| commit | ff4b6bf7eef4f5b921eed78f2816abcc55bcdd68 (patch) | |
| tree | fd779a4c49cbb036ae897c62c1bc692e807600e1 | |
| parent | 5a741f8cc6fe62542f955cd8d24933a1b6589cbd (diff) | |
| download | linux-ff4b6bf7eef4f5b921eed78f2816abcc55bcdd68.tar.xz | |
riscv: dts: microchip: add can resets to mpfs
The can IP on PolarFire SoC requires the use of the blocks reset
during normal operation, and the property is therefore required by the
binding, causing a warning on the m100pfsevp board where it is default
enabled:
mpfs-m100pfsevp.dtb: can@2010c000 (microchip,mpfs-can): 'resets' is a required property
Add the reset to both can nodes.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..bd658f3a8b1d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -425,6 +425,7 @@ clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; + resets = <&mss_top_sysreg CLK_CAN0>; status = "disabled"; }; @@ -434,6 +435,7 @@ clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; + resets = <&mss_top_sysreg CLK_CAN1>; status = "disabled"; }; |