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authorJani Nikula <jani.nikula@intel.com>2025-12-31 14:26:09 +0300
committerJani Nikula <jani.nikula@intel.com>2026-01-02 13:17:24 +0300
commitfcb6fc87f1a189c4b0141513556ed01419f4d90e (patch)
tree5593a7fa3257cfc6e9c2db94940c3830ce17f977
parent0eccf37660aebf9be4b35dac6c30ae729c42a720 (diff)
downloadlinux-fcb6fc87f1a189c4b0141513556ed01419f4d90e.tar.xz
drm/i915/gvt: reduce include of gt/intel_engine_regs.h
Move IS_RESTORE_INHIBIT() to scheduler.c, along with the gt/intel_engine_regs.h include. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/2f5440016b5d164a6f3889565761caa17cccd4b7.1767180318.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c1
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio_context.h5
-rw-r--r--drivers/gpu/drm/i915/gvt/scheduler.c4
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 68afd9b046d4..bd20f287720f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -61,6 +61,7 @@
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt_regs.h"
#include "display_helpers.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h
index a821edf574dd..c0e3695e3bbe 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
@@ -38,8 +38,6 @@
#include <linux/types.h>
-#include "gt/intel_engine_regs.h"
-
struct i915_request;
struct intel_context;
struct intel_engine_cs;
@@ -57,7 +55,4 @@ bool is_inhibit_context(struct intel_context *ce);
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
struct i915_request *req);
-#define IS_RESTORE_INHIBIT(a) \
- IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
-
#endif
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 6b5ee40a4386..15fdd514ca83 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -40,6 +40,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_execlists_submission.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc.h"
@@ -54,6 +55,9 @@
#define RING_CTX_OFF(x) \
offsetof(struct execlist_ring_context, x)
+#define IS_RESTORE_INHIBIT(a) \
+ IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
+
static void set_context_pdp_root_pointer(
struct execlist_ring_context *ring_context,
u32 pdp[8])