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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2023-02-22 06:49:39 +0300
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2023-03-25 23:38:10 +0300
commitfb97147ad2956cff0e9fa2f6407c93bc9242db9b (patch)
tree6285e0bb9f5ac0aa21556f411b25ceb621381d90
parentec1c6ff81e8e2123b4d727b2b9ac74049b7c2b52 (diff)
downloadlinux-fb97147ad2956cff0e9fa2f6407c93bc9242db9b.tar.xz
drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3
The ESCR and OTAR registers are not present in all DU channels on Gen3 SoCs. ESCR only exists in channels that can be routed to an LVDS or DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing those registers for other channels. This replaces the DU gen check, as Gen4 doesn't have LVDS or DPAD outputs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_crtc.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 5e552b326162..d6d29be6b4f4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -298,13 +298,26 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
escr = params.escr;
}
- if (rcdu->info->gen < 4) {
+ /*
+ * The ESCR register only exists in DU channels that can output to an
+ * LVDS or DPAT, and the OTAR register in DU channels that can output
+ * to a DPAD.
+ */
+ if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
+ rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs |
+ rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs |
+ rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) &
+ BIT(rcrtc->index)) {
dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
- rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
}
+ if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
+ rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
+ BIT(rcrtc->index))
+ rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
+
/* Signal polarities */
dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)