diff options
| author | Han Gao <rabenda.cn@gmail.com> | 2025-09-18 23:44:49 +0300 |
|---|---|---|
| committer | Drew Fustini <fustini@kernel.org> | 2025-10-17 21:32:41 +0300 |
| commit | fac4be7b3d49ae7e32d8ae523343d7fe790772f9 (patch) | |
| tree | 2b1e0428e3025481a9f363920366738baae461fb | |
| parent | bcc3b9c5de5e2a03ede1a8133c05255927d744d6 (diff) | |
| download | linux-fac4be7b3d49ae7e32d8ae523343d7fe790772f9.tar.xz | |
riscv: dts: thead: add zfh for th1520
th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.
commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042")
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
| -rw-r--r-- | arch/riscv/boot/dts/thead/th1520.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8e50e24040c2..dfc868e5b19a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -26,7 +26,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <0>; @@ -53,7 +53,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <1>; @@ -80,7 +80,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <2>; @@ -107,7 +107,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <3>; |