diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-01-22 07:48:58 +0300 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-01-27 06:03:33 +0300 |
| commit | f86bed1bc93111a0308bc4d0335ee68d6fc9a1f4 (patch) | |
| tree | d3b47b41234e08d505149a6ff8a96b113776352c | |
| parent | cca7eda1c73045d6fb12b3db34f90de65412e742 (diff) | |
| download | linux-f86bed1bc93111a0308bc4d0335ee68d6fc9a1f4.tar.xz | |
drm/i915/cx0: Clear response ready & error bit
Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS
before writing the transaction pending bit of
PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done
we find that the PHY hangs since it ends up in a weird state if left
idle for more than 1 hour.
Bspec: 65101
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260122044859.753682-1-suraj.kandpal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4f56a370102d..ff74f64eb970 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -223,6 +223,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder, return -ETIMEDOUT; } + intel_clear_response_ready_flag(encoder, lane); + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | XELPDP_PORT_M2P_COMMAND_READ | @@ -294,6 +296,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder, return -ETIMEDOUT; } + intel_clear_response_ready_flag(encoder, lane); + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED : |