diff options
| author | Luca Coelho <luciano.coelho@intel.com> | 2026-03-24 11:04:28 +0300 |
|---|---|---|
| committer | Luca Coelho <luciano.coelho@intel.com> | 2026-03-25 08:57:11 +0300 |
| commit | f86b08bf1766e9883bc75a66aeca7d737bf4c093 (patch) | |
| tree | b5c822910a8906bfa74636df03541929f7daf88f | |
| parent | cf37495ad17db876c28a824c003133c2e103cd59 (diff) | |
| download | linux-f86b08bf1766e9883bc75a66aeca7d737bf4c093.tar.xz | |
drm/i915: move CNP clock gating init into intel_pch
Move the CNP PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding
CFL/CML caller to the display-specific code.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-5-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_pch.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_clock_gating.c | 13 |
2 files changed, 11 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c index b7fade66b1da..d2c1b1751838 100644 --- a/drivers/gpu/drm/i915/display/intel_pch.c +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -279,6 +279,13 @@ static void intel_pch_lpt_init_clock_gating(struct intel_display *display) TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); } +static void intel_pch_cnp_init_clock_gating(struct intel_display *display) +{ + /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */ + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, + CNP_PWM_CGE_GATING_DISABLE); +} + void intel_pch_init_clock_gating(struct intel_display *display) { switch (INTEL_PCH_TYPE(display)) { @@ -292,6 +299,9 @@ void intel_pch_init_clock_gating(struct intel_display *display) case PCH_LPT_LP: intel_pch_lpt_init_clock_gating(display); break; + case PCH_CNP: + intel_pch_cnp_init_clock_gating(display); + break; default: break; } diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 4c19028a9e20..ee2489a2fbe7 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -299,20 +299,9 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915) SGSI_SIDECLK_DIS); } -static void cnp_init_clock_gating(struct drm_i915_private *i915) -{ - struct intel_display *display = i915->display; - - if (!HAS_PCH_CNP(display)) - return; - - /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */ - intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); -} - static void cfl_init_clock_gating(struct drm_i915_private *i915) { - cnp_init_clock_gating(i915); + intel_pch_init_clock_gating(i915->display); gen9_init_clock_gating(i915); /* WAC6entrylatency:cfl */ |