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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2025-03-29 15:12:56 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-22 12:15:13 +0300 |
| commit | f7a98e256ee30f50de1e7b43cc383828834e8c9e (patch) | |
| tree | 0246c241597eb623f85301b9f78709b9f1bc9890 | |
| parent | 03a45e17e636ee1962d8c175c12a0ff48a0b7ccd (diff) | |
| download | linux-f7a98e256ee30f50de1e7b43cc383828834e8c9e.tar.xz | |
arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol
Add a device node for I2C2 pincontrol. Also enable the I2C2 device node
with 1MHz clock frequency as it is connected to the RAA215300 PMIC on
the RZ/G3E SoM.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250329121258.172099-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 72b42a81bcf3..ca56a9edda2e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -18,6 +18,7 @@ compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; aliases { + i2c2 = &i2c2; mmc0 = &sdhi0; mmc2 = &sdhi2; }; @@ -51,7 +52,19 @@ clock-frequency = <48000000>; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <1000000>; + status = "okay"; +}; + &pinctrl { + i2c2_pins: i2c { + pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */ + <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */ + }; + sdhi0_emmc_pins: sd0-emmc { sd0-ctrl { pins = "SD0CLK", "SD0CMD"; |