diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-12-20 01:12:30 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-02-12 21:53:07 +0400 |
| commit | f1ff6965e7ae5b5312ebba280570545f05409244 (patch) | |
| tree | 2cdbb05a0b54915aed4fee1ca9cb57efa3dc56b8 | |
| parent | 851855d8573fc0b9f30901980001d6374d92653e (diff) | |
| download | linux-f1ff6965e7ae5b5312ebba280570545f05409244.tar.xz | |
drm/i915: don't wait for vblank after enabling pipe on HSW
Because on Haswell, the pipe is never running at this point, so we hit
the 50ms timeout waiting for nothing. We already have two other places
where we wait for vblanks on haswell_crtc_enable, so we're safe.
This gets us rid of one instance of "vblank wait timed out" for each
mode set, which means driver init and resume are also 50ms faster.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c456768282da..0523419bc485 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3747,7 +3747,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, - intel_crtc->config.has_pch_encoder, false, true); + intel_crtc->config.has_pch_encoder, false, false); if (intel_crtc->config.has_pch_encoder) lpt_pch_enable(crtc); |