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authordevi priya <quic_devipriy@quicinc.com>2024-05-16 06:24:34 +0300
committerVinod Koul <vkoul@kernel.org>2024-06-03 17:02:32 +0300
commitf1aaa788b997ba8a7810da0696e89fd3f79ecce3 (patch)
tree90be4016c0315cbe4b44b11460aabce4527721ed
parent29f09daab910c797f5468afda91a51e3e29de7ee (diff)
downloadlinux-f1aaa788b997ba8a7810da0696e89fd3f79ecce3.tar.xz
phy: qcom-qmp: Add missing offsets for Qserdes PLL registers.
Add missing register offsets for Qserdes PLL. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
-rw-r--r--drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
index ad326e301a3a..231e59364e31 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
@@ -8,6 +8,9 @@
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_EN_CENTER 0x010
+#define QSERDES_PLL_SSC_ADJ_PER1 0x014
+#define QSERDES_PLL_SSC_ADJ_PER2 0x018
#define QSERDES_PLL_SSC_PER1 0x01c
#define QSERDES_PLL_SSC_PER2 0x020
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024