diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-12-08 21:26:24 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-01-23 06:20:27 +0300 |
| commit | f1640f9d7fa44b19f06aa0e9b2e99bdd8e62863a (patch) | |
| tree | 7527c9067ddc3f967f6ab4a68147fb1199b5f4d9 | |
| parent | 46ccf3fb55d5260e6e3535fec7bcb85f3e9ba667 (diff) | |
| download | linux-f1640f9d7fa44b19f06aa0e9b2e99bdd8e62863a.tar.xz | |
drm/i915/vga: Clean up VGA registers even if VGA plane is disabled
Turns out at least some systems (eg. HSW Lenovo ThinkCentre E73)
configure the VGA registers even when booting in UEFI mode. So
in order to avoid any issues with the MSR register we should
clean up the VGA registers anyway.
For now this mostly avoids the potential for unclaimed register
accesses due to the power well vs. MDA/CGA selection. But this
will become more important soon as we'll start to rely on the
MSR register to control VGA memory decode as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-7-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vga.c | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 744812260ae3..6a19fb242248 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -63,7 +63,6 @@ void intel_vga_disable(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); i915_reg_t vga_reg = intel_vga_cntrl_reg(display); - enum pipe pipe; u8 msr, sr1; u32 tmp; @@ -79,18 +78,33 @@ void intel_vga_disable(struct intel_display *display) } tmp = intel_de_read(display, vga_reg); - if (tmp & VGA_DISP_DISABLE) - return; - if (display->platform.cherryview) - pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); - else if (has_vga_pipe_sel(display)) - pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); - else - pipe = PIPE_A; + if ((tmp & VGA_DISP_DISABLE) == 0) { + enum pipe pipe; + + if (display->platform.cherryview) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); + else if (has_vga_pipe_sel(display)) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); + else + pipe = PIPE_A; + + drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", + pipe_name(pipe)); + } else { + drm_dbg_kms(display->drm, "VGA plane is disabled\n"); - drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", - pipe_name(pipe)); + /* + * Unfortunately at least some BIOSes (eg. HSW Lenovo + * ThinkCentre E73) set up the VGA registers even when + * in UEFI mode with the VGA plane disabled. So we need to + * always clean up the mess for iGPUs. For discrete GPUs we + * don't really care about the state of the VGA registers + * since all VGA accesses can be blocked via the bridge. + */ + if (display->platform.dgfx) + goto reset_vgacntr; + } /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |