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| author | Oliver Upton <oliver.upton@linux.dev> | 2025-03-05 23:26:31 +0300 |
|---|---|---|
| committer | Oliver Upton <oliver.upton@linux.dev> | 2025-03-11 22:52:32 +0300 |
| commit | ed335722b4571c438c008fc96bf86b9d4705a60f (patch) | |
| tree | 628727fc9a0d9cfaded2cce89ba77125466543aa | |
| parent | 93b01528586b693a3ab31ed7be92b2347a9416ca (diff) | |
| download | linux-ed335722b4571c438c008fc96bf86b9d4705a60f.tar.xz | |
KVM: arm64: Always support SW_INCR PMU event
Support for SW_INCR is unconditional, as KVM traps accesses to
PMSWINC_EL0 and emulates the intended event increment. While it is
expected that ~all PMUv3 implementations already advertise this event,
non-PMUv3 hardware may not.
Tested-by: Janne Grunau <j@jannau.net>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250305202641.428114-5-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
| -rw-r--r-- | arch/arm64/kvm/pmu-emul.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 104672a0c5a2..62349b670cf9 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -856,6 +856,8 @@ static u64 compute_pmceid0(struct arm_pmu *pmu) { u64 val = __compute_pmceid(pmu, 0); + /* always support SW_INCR */ + val |= BIT(ARMV8_PMUV3_PERFCTR_SW_INCR); /* always support CHAIN */ val |= BIT(ARMV8_PMUV3_PERFCTR_CHAIN); return val; |