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| author | Ovidiu Panait <ovidiu.panait.rb@renesas.com> | 2025-12-09 12:11:14 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-12-29 13:43:22 +0300 |
| commit | ebb3acf4d7c95b52265084168b59a565bf972883 (patch) | |
| tree | 41c1257cfe9a02b18eb55ec0a96f3f3142be8c6c | |
| parent | 2efea3b35cc916f04f06b89f2e2557dbd9c48109 (diff) | |
| download | linux-ebb3acf4d7c95b52265084168b59a565bf972883.tar.xz | |
clk: renesas: r9a09g056: Add clock and reset entries for TSU
Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a09g056-cpg.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c index 741df446e24e..d831246ff55d 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -537,6 +537,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, BUS_MSTOP(3, BIT(4))), + DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9, + BUS_MSTOP(5, BIT(2))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; static const struct rzv2h_reset r9a09g056_resets[] __initconst = { @@ -626,6 +630,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ + DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = { |