diff options
| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-02-04 15:40:08 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-06 14:01:34 +0300 |
| commit | eb4262203d7d85eb7b6f2696816db272e41f5464 (patch) | |
| tree | dc4dd81dbd65d04bbe71e3a4bd2e99f4b196bac4 | |
| parent | d0f17738778c12be629ba77ff00c43c3e9eb8428 (diff) | |
| download | linux-eb4262203d7d85eb7b6f2696816db272e41f5464.tar.xz | |
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 1d299c99b4e7..c53cd90d4112 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1261,14 +1261,16 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy_hdmi0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; |