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| author | Paul Kocialkowski <paulk@sys-base.io> | 2025-07-04 18:40:07 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2025-07-14 06:51:14 +0300 |
| commit | e8ab346f9907a1a3aa2f0e5decf849925c06ae2e (patch) | |
| tree | 08e6af0c9a0c152a276fdca9ee1ea404367ed09d | |
| parent | c17b1b6c86059664e91008a23547ef0aadfc2228 (diff) | |
| download | linux-e8ab346f9907a1a3aa2f0e5decf849925c06ae2e.tar.xz | |
clk: sunxi-ng: v3s: Fix de clock definition
The de clock is marked with CLK_SET_RATE_PARENT, which is really not
necessary (as confirmed from experimentation) and significantly
restricts flexibility for other clocks using the same parent.
In addition the source selection (parent) field is marked as using
2 bits, when it the documentation reports that it uses 3.
Fix both issues in the de clock definition.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Link: https://patch.msgid.link/20250704154008.3463257-1-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 579a81bb46df..7744fc632ea6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -347,8 +347,7 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", static const char * const de_parents[] = { "pll-video", "pll-periph0" }; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, - 0x104, 0, 4, 24, 2, BIT(31), - CLK_SET_RATE_PARENT); + 0x104, 0, 4, 24, 3, BIT(31), 0); static const char * const tcon_parents[] = { "pll-video" }; static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, |