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| author | Matt Roper <matthew.d.roper@intel.com> | 2026-02-06 00:41:41 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-02-06 20:49:20 +0300 |
| commit | e8100643ff01be0fc74048b8296cfb2b9b5c90ed (patch) | |
| tree | e6fcdd9fa86a010ecbef1078b50367716913d6bc | |
| parent | 6acf3d3ed6c1f0febdd046578ea9cafcd47912f4 (diff) | |
| download | linux-e8100643ff01be0fc74048b8296cfb2b9b5c90ed.tar.xz | |
drm/xe/xe3p_xpc: XeCore mask spans four registers
On Xe3p_XPC, there are now four registers reserved to express the XeCore
mask rather than just three. Define the new registers and update the IP
descriptor accordingly.
Note that this only applies to Xe3p_XPC for now; Xe3p_LPG still only
uses three registers to express the mask.
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260205214139.48515-4-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_topology.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_types.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pci.c | 4 |
4 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 7d3ec1fe4f7f..52440100a731 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -253,6 +253,8 @@ #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) +#define XE3P_XPC_GT_GEOMETRY_DSS_3 XE_REG(0x915c) +#define XE3P_XPC_GT_COMPUTE_DSS_3 XE_REG(0x9160) #define SERVICE_COPY_ENABLE XE_REG(0x9170) #define FUSE_SERVICE_COPY_ENABLE_MASK REG_GENMASK(7, 0) diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c index 575dcfd5eb9d..bfe87e682879 100644 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@ -212,11 +212,13 @@ xe_gt_topology_init(struct xe_gt *gt) XELP_GT_GEOMETRY_DSS_ENABLE, XE2_GT_GEOMETRY_DSS_1, XE2_GT_GEOMETRY_DSS_2, + XE3P_XPC_GT_GEOMETRY_DSS_3, }; static const struct xe_reg compute_regs[] = { XEHP_GT_COMPUTE_DSS_ENABLE, XEHPC_GT_COMPUTE_DSS_ENABLE_EXT, XE2_GT_COMPUTE_DSS_2, + XE3P_XPC_GT_COMPUTE_DSS_3, }; struct drm_printer p; diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 44a4e7af11b1..caf7e7e78be9 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -35,7 +35,7 @@ enum xe_gt_eu_type { XE_GT_EU_TYPE_SIMD16, }; -#define XE_MAX_DSS_FUSE_REGS 3 +#define XE_MAX_DSS_FUSE_REGS 4 #define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS) #define XE_MAX_EU_FUSE_REGS 1 #define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 02c192831323..aec386c5ca9a 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -122,8 +122,8 @@ static const struct xe_graphics_desc graphics_xe3p_xpc = { GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE), - .num_geometry_xecore_fuse_regs = 3, - .num_compute_xecore_fuse_regs = 3, + .num_geometry_xecore_fuse_regs = 4, + .num_compute_xecore_fuse_regs = 4, }; static const struct xe_media_desc media_xem = { |