ALSA: pcxhr: Share PLL frequency register calculation

The PCXHR and HR222 clock paths duplicate the PLL divider calculation and
register encoding. The HR222 variant extends the same format with an
additional range for rates above those supported by the older boards.

Move the complete encoding into pcxhr_pll_freq_register() and pass each
hardware path its existing maximum frequency. The additional encoding
branch is unreachable with the older 110 kHz limit, so this preserves both
paths' accepted ranges and generated register values while removing the
duplicate implementation and its long-standing TODO.

Signed-off-by: Cássio Gabriel <cassiogabrielcontato@gmail.com>
Link: https://patch.msgid.link/20260612-alsa-pcxhr-pll-helper-v1-1-c84ae2bd2e9b@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>

3 files changed, 12 insertions, 36 deletions

diff --git a/sound/pci/pcxhr/pcxhr.c b/sound/pci/pcxhr/pcxhr.c
index 1eea40e94c43..25a640304430 100644
--- a/sound/pci/pcxhr/pcxhr.c
+++ b/sound/pci/pcxhr/pcxhr.c
@@ -180,16 +180,18 @@ static const struct board_parameters pcxhr_board_params[] = {
 				      (x->fw_file_set == 0)   || \
 				      (x->fw_file_set == 2))
 
-static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
-				   unsigned int* realfreq)
+int pcxhr_pll_freq_register(unsigned int freq, unsigned int max_freq,
+			    unsigned int *pllreg, unsigned int *realfreq)
 {
 	unsigned int reg;
 
-	if (freq < 6900 || freq > 110000)
+	if (freq < 6900 || freq > max_freq)
 		return -EINVAL;
 	reg = (28224000 * 2) / freq;
 	reg = (reg - 1) / 2;
-	if (reg < 0x200)
+	if (reg < 0x100)
+		*pllreg = reg + 0xc00;
+	else if (reg < 0x200)
 		*pllreg = reg + 0x800;
 	else if (reg < 0x400)
 		*pllreg = reg & 0x1ff;
@@ -260,7 +262,8 @@ static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
 		default :
 			val = PCXHR_FREQ_PLL;
 			/* get the value for the pll register */
-			err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
+			err = pcxhr_pll_freq_register(rate, 110000, &pllreg,
+						      &realfreq);
 			if (err)
 				return err;
 			pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
diff --git a/sound/pci/pcxhr/pcxhr.h b/sound/pci/pcxhr/pcxhr.h
index 1b85200d00dd..011227b1fe79 100644
--- a/sound/pci/pcxhr/pcxhr.h
+++ b/sound/pci/pcxhr/pcxhr.h
@@ -190,6 +190,8 @@ struct pcxhr_hostport
 };
 
 /* exported */
+int pcxhr_pll_freq_register(unsigned int freq, unsigned int max_freq,
+			    unsigned int *pllreg, unsigned int *realfreq);
 int pcxhr_create_pcm(struct snd_pcxhr *chip);
 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate);
 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
diff --git a/sound/pci/pcxhr/pcxhr_mix22.c b/sound/pci/pcxhr/pcxhr_mix22.c
index 80d22e22ea30..76beb443d983 100644
--- a/sound/pci/pcxhr/pcxhr_mix22.c
+++ b/sound/pci/pcxhr/pcxhr_mix22.c
@@ -305,36 +305,6 @@ int hr222_sub_init(struct pcxhr_mgr *mgr)
 }
 
 
-/* calc PLL register */
-/* TODO : there is a very similar fct in pcxhr.c */
-static int hr222_pll_freq_register(unsigned int freq,
-				   unsigned int *pllreg,
-				   unsigned int *realfreq)
-{
-	unsigned int reg;
-
-	if (freq < 6900 || freq > 219000)
-		return -EINVAL;
-	reg = (28224000 * 2) / freq;
-	reg = (reg - 1) / 2;
-	if (reg < 0x100)
-		*pllreg = reg + 0xC00;
-	else if (reg < 0x200)
-		*pllreg = reg + 0x800;
-	else if (reg < 0x400)
-		*pllreg = reg & 0x1ff;
-	else if (reg < 0x800) {
-		*pllreg = ((reg >> 1) & 0x1ff) + 0x200;
-		reg &= ~1;
-	} else {
-		*pllreg = ((reg >> 2) & 0x1ff) + 0x400;
-		reg &= ~3;
-	}
-	if (realfreq)
-		*realfreq = (28224000 / (reg + 1));
-	return 0;
-}
-
 int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
 			unsigned int rate,
 			int *changed)
@@ -345,7 +315,8 @@ int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
 
 	switch (mgr->use_clock_type) {
 	case HR22_CLOCK_TYPE_INTERNAL:
-		err = hr222_pll_freq_register(rate, &pllreg, &realfreq);
+		err = pcxhr_pll_freq_register(rate, 219000,
+					      &pllreg, &realfreq);
 		if (err)
 			return err;