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authorAlex Deucher <alexander.deucher@amd.com>2015-03-03 04:36:26 +0300
committerZefan Li <lizefan@huawei.com>2015-06-19 06:40:20 +0300
commite653b3ede2c327db4310f8053286521e471c9c0a (patch)
treed7a277b0d5af6cccbaa75f7714288377b4ba6f05
parentba4e25ac180d5903320c42e4ef792e86c406fbfb (diff)
downloadlinux-e653b3ede2c327db4310f8053286521e471c9c0a.tar.xz
drm/radeon: do a posting read in r100_set_irq
commit f957063fee6392bb9365370db6db74dc0b2dce0a upstream. To make sure the writes go through the pci bridge. bug: https://bugzilla.kernel.org/show_bug.cgi?id=90741 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Zefan Li <lizefan@huawei.com>
-rw-r--r--drivers/gpu/drm/radeon/r100.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 40ed0e5b95a3..8ec5b8553873 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -726,6 +726,10 @@ int r100_irq_set(struct radeon_device *rdev)
tmp |= RADEON_FP2_DETECT_MASK;
}
WREG32(RADEON_GEN_INT_CNTL, tmp);
+
+ /* read back to post the write */
+ RREG32(RADEON_GEN_INT_CNTL);
+
return 0;
}