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| author | Stefano Radaelli <stefano.radaelli21@gmail.com> | 2025-12-15 00:52:53 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2025-12-30 11:03:51 +0300 |
| commit | e583afbe3568c654a221793019e77738ffd2946f (patch) | |
| tree | 170b08bda1fe3147f2cb091b25d8c9e66f403c7a | |
| parent | cb452cc24ade40ebf3f0c592e1bad17c1b3cd693 (diff) | |
| download | linux-e583afbe3568c654a221793019e77738ffd2946f.tar.xz | |
arm64: dts: imx8mp-var-som: Add support for TSC2046 touchscreen
The VAR-SOM-MX8MP integrates a TSC2046 resistive touchscreen controller.
The controller is physically located on the SOM, and its signals are
routed to the SOM pins, allowing carrier boards to make use of it.
This patch adds the TSC2046 node and the appropriate SPI controller.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 6da5df11c44a..49467b48d0b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -100,6 +100,37 @@ cpu-supply = <&buck2>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + tsc2046: touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -347,6 +378,15 @@ >; }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x12 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -381,6 +421,12 @@ >; }; + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xc0 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 |