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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-10-15 22:26:09 +0300
committerBiju Das <biju.das.jz@bp.renesas.com>2025-12-16 10:24:37 +0300
commitddeb8d5c1f97d9112b93a779c9e3dc3eaab68c19 (patch)
tree421bc40ad261985f806461a389e779349d94fe4b
parent2359fe93138d80ca378072d4c743b8c17612f3e3 (diff)
downloadlinux-ddeb8d5c1f97d9112b93a779c9e3dc3eaab68c19.tar.xz
dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N
Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, the RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and requires five clocks instead of six. To reflect these hardware differences, update the binding schema to support the reduced clock and reset requirements for RZ/V2H(P). Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is reused for RZ/V2N. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251015192611.241920-6-prabhakar.mahadev-lad.rj@bp.renesas.com
-rw-r--r--Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml120
1 files changed, 91 insertions, 29 deletions
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
index 5a99d9b9635e..c20625b8425e 100644
--- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -14,16 +14,21 @@ description: |
RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
up to four data lanes.
-allOf:
- - $ref: /schemas/display/dsi-controller.yaml#
-
properties:
compatible:
- items:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+ - renesas,r9a07g054-mipi-dsi # RZ/V2L
+ - const: renesas,rzg2l-mipi-dsi
+
+ - items:
+ - const: renesas,r9a09g056-mipi-dsi # RZ/V2N
+ - const: renesas,r9a09g057-mipi-dsi
+
- enum:
- - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
- - renesas,r9a07g054-mipi-dsi # RZ/V2L
- - const: renesas,rzg2l-mipi-dsi
+ - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
reg:
maxItems: 1
@@ -49,34 +54,56 @@ properties:
- const: debug
clocks:
- items:
- - description: DSI D-PHY PLL multiplied clock
- - description: DSI D-PHY system clock
- - description: DSI AXI bus clock
- - description: DSI Register access clock
- - description: DSI Video clock
- - description: DSI D-PHY Escape mode transmit clock
+ oneOf:
+ - items:
+ - description: DSI D-PHY PLL multiplied clock
+ - description: DSI D-PHY system clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
+ - items:
+ - description: DSI D-PHY PLL reference clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
clock-names:
- items:
- - const: pllclk
- - const: sysclk
- - const: aclk
- - const: pclk
- - const: vclk
- - const: lpclk
+ oneOf:
+ - items:
+ - const: pllclk
+ - const: sysclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
+ - items:
+ - const: pllrefclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
resets:
- items:
- - description: MIPI_DSI_CMN_RSTB
- - description: MIPI_DSI_ARESET_N
- - description: MIPI_DSI_PRESET_N
+ oneOf:
+ - items:
+ - description: MIPI_DSI_CMN_RSTB
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
+ - items:
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
reset-names:
- items:
- - const: rst
- - const: arst
- - const: prst
+ oneOf:
+ - items:
+ - const: rst
+ - const: arst
+ - const: prst
+ - items:
+ - const: arst
+ - const: prst
power-domains:
maxItems: 1
@@ -130,6 +157,41 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-mipi-dsi
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ maxItems: 5
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ maxItems: 2
+ else:
+ properties:
+ clocks:
+ minItems: 6
+
+ clock-names:
+ minItems: 6
+
+ resets:
+ minItems: 3
+
+ reset-names:
+ minItems: 3
+
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>