diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-05-20 14:51:41 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-31 11:52:23 +0300 |
| commit | dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb (patch) | |
| tree | 3cff2fc42dd004a856489721e4cdbc726c89d1c1 | |
| parent | 1b3c392bd655af31a414fc82382cec13e090a997 (diff) | |
| download | linux-dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb.tar.xz | |
arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device
tree, increasing performance by ca. 33%.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 587fab0ceb3f..f689996b5808 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1182,6 +1182,7 @@ <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -1198,6 +1199,7 @@ <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G054_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled"; |