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| author | Harini T <harini.t@amd.com> | 2026-01-09 09:22:59 +0300 |
|---|---|---|
| committer | Jassi Brar <jassisinghbrar@gmail.com> | 2026-01-25 03:42:39 +0300 |
| commit | dac2b98ede6c29f01dec95e88fef59e5138bd3a4 (patch) | |
| tree | bb666e7997f475d06ffb1a193e5c5a9b6f732acd | |
| parent | 6acf50c7f0ba4fcc048bd9018080fa53844c5705 (diff) | |
| download | linux-dac2b98ede6c29f01dec95e88fef59e5138bd3a4.tar.xz | |
dt-bindings: mailbox: xlnx,zynqmp-ipi-mailbox: Document msg region requirement
Add description clarifying that for Versal IPI mailboxes, both host and
remote agents must have the "msg" register region defined for successful
message passing. Without both, only notification-based communication
works.
Signed-off-by: Harini T <harini.t@amd.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml index 04d6473d666f..a5205ee5ad0f 100644 --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml @@ -11,6 +11,17 @@ description: | messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI agent owns registers used for notification and buffers for message. + For Versal devices, there are two types of IPI channels: + - Buffered channels: Support message passing and require the "msg" + register region to be present on both the host and remote IPI agents. + - Buffer-less channels: Support notification only and do not require the + "msg" register region. For these channels, the "msg" region should be + omitted. + + For message passing, both the host and remote IPI agents must define the "msg" + register region. If either agent omits the "msg" region, only notification + based communication is possible. + +-------------------------------------+ | Xilinx ZynqMP IPI Controller | +-------------------------------------+ |