diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-04-30 12:34:09 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-11 12:07:07 +0300 |
| commit | da4a37540b780c386eb2362bfcc638f769918cb1 (patch) | |
| tree | 81ab96ed9aeeb514d33ab68fb0d9a7fc6dab0f0c | |
| parent | bbe2277dedbeb54bb251ae3e0599007253739aad (diff) | |
| download | linux-da4a37540b780c386eb2362bfcc638f769918cb1.tar.xz | |
pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match
The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The
existing greater-than comparison against oen_max_pin in
rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value
rather than enforcing the single valid OEN pin for each SoC. Replace the
range check with an exact equality test so that only the designated OEN
pin is accepted.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 7b1bb66d4ff6..2a46ba7b3709 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1124,7 +1124,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); - if (pin > pctrl->data->hwcfg->oen_max_pin) + if (pin != pctrl->data->hwcfg->oen_max_pin) return -EINVAL; /* |