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authorMarc Zyngier <maz@kernel.org>2026-01-08 20:32:28 +0300
committerMarc Zyngier <maz@kernel.org>2026-01-15 14:58:57 +0300
commitd78a14decd494caf72ea0144624621e7e43ae451 (patch)
tree19919e5518ff247d8a5474bdc0542dcbf945454d
parent19f75678238734ef383f9e10d8e1020873e97170 (diff)
downloadlinux-d78a14decd494caf72ea0144624621e7e43ae451.tar.xz
KVM: arm64: Handle FEAT_IDST for sysregs without specific handlers
Add a bit of infrastrtcture to triage_sysreg_trap() to handle the case of registers falling into the Feature ID space that do not have a local handler. For these, we can directly apply the FEAT_IDST semantics and inject an EC=0x18 exception. Otherwise, an UNDEF will do. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Reviewed-by: Yuan Yao <yaoyuan@linux.alibaba.com> Link: https://patch.msgid.link/20260108173233.2911955-5-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
-rw-r--r--arch/arm64/kvm/emulate-nested.c13
-rw-r--r--arch/arm64/kvm/sys_regs.h10
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 616eb6ad6870..4aabd624c4be 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -2589,6 +2589,19 @@ local:
params = esr_sys64_to_params(esr);
/*
+ * This implements the pseudocode UnimplementedIDRegister()
+ * helper for the purpose of dealing with FEAT_IDST.
+ */
+ if (in_feat_id_space(&params)) {
+ if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP))
+ kvm_inject_sync(vcpu, kvm_vcpu_get_esr(vcpu));
+ else
+ kvm_inject_undefined(vcpu);
+
+ return true;
+ }
+
+ /*
* Check for the IMPDEF range, as per DDI0487 J.a,
* D18.3.2 Reserved encodings for IMPLEMENTATION
* DEFINED registers.
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index b3f904472fac..2a983664220c 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -49,6 +49,16 @@ struct sys_reg_params {
.Op2 = ((esr) >> 17) & 0x7, \
.is_write = !((esr) & 1) })
+/*
+ * The Feature ID space is defined as the System register space in AArch64
+ * with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.
+ */
+static inline bool in_feat_id_space(struct sys_reg_params *p)
+{
+ return (p->Op0 == 3 && !(p->Op1 & 0b100) && p->Op1 != 2 &&
+ p->CRn == 0 && !(p->CRm & 0b1000));
+}
+
struct sys_reg_desc {
/* Sysreg string for debug */
const char *name;