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authorRoger Quadros <rogerq@kernel.org>2022-06-28 15:22:53 +0300
committerVinod Koul <vkoul@kernel.org>2022-08-30 08:12:57 +0300
commitd5f2e7475f718e3ea47953baffc3e65e07b9272b (patch)
tree34711b3790df2d039813b81f2b0f2516974fe3e9
parent1aa54982bc2d5cd7e52bb6807ac46f8018a832ee (diff)
downloadlinux-d5f2e7475f718e3ea47953baffc3e65e07b9272b.tar.xz
dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
ti,j7200-wiz-10g supports an additional reference clock. Add compatible and the additional clock. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-6-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml21
1 files changed, 20 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3127bb648427..8305654b66c9 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -16,19 +16,23 @@ properties:
- ti,j721e-wiz-16g
- ti,j721e-wiz-10g
- ti,am64-wiz-10g
+ - ti,j7200-wiz-10g
power-domains:
maxItems: 1
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
description: clock-specifier to represent input to the WIZ
clock-names:
+ minItems: 3
items:
- const: fck
- const: core_ref_clk
- const: ext_ref_clk
+ - const: core_ref1_clk
num-lanes:
minimum: 1
@@ -106,6 +110,11 @@ properties:
- assigned-clocks
- assigned-clock-parents
+ ti,scm:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to System Control Module for syscon regmap access.
+
patternProperties:
"^pll[0|1]-refclk$":
type: object
@@ -173,6 +182,16 @@ required:
- "#reset-cells"
- ranges
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j7200-wiz-10g
+ then:
+ required:
+ - ti,scm
+
additionalProperties: false
examples: