clk: imx: imx6ul: change flexcan clock to support CiA bitrates

Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
frequency from 30MHz to 40MHz which allows to support all bitrates recommended
by CiA.

The patch sets CAN_CLK_SEL to 80MHz by changing its clock parent from
CLK_PLL3_60M to CLK_PLL3_80M. The post-divider CAN_CLK_PODF is set to /2 by
default which makes 40MHz CAN_CLK_ROOT from its parent CAN_CLK_SEL.

Background:
CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50,
125, 250, 500, 800 and 1000kbit/s.

With the flexcan serial clock at 30MHz (original value) setting some common
bitrates ("ip link set canX type can bitrate <bitrate>") gives the following
results:
requested value / actually set value
5000: bitrate 5000 sample-point 0.708
10000: bitrate 10000 sample-point 0.866
20000: bitrate 20000 sample-point 0.866
40000: bitrate 40000 sample-point 0.866
50000: bitrate 50000 sample-point 0.866
80000: bitrate 80000 sample-point 0.866
100000: bitrate 100000 sample-point 0.866
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.866
400000: bitrate 400000 sample-point 0.866
500000: bitrate 500000 sample-point 0.866
666666: bitrate 666666 sample-point 0.800
800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3%
1000000: bitrate 1000000 sample-point 0.733

With the flexcan serial clock at 40MHz (new value) we get this:
5000: no more possible
10000: bitrate 10000 sample-point 0.875
20000: bitrate 20000 sample-point 0.875
40000: bitrate 40000 sample-point 0.850
50000: bitrate 50000 sample-point 0.875
80000: bitrate 80000 sample-point 0.850
100000: bitrate 100000 sample-point 0.875
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.875
400000: bitrate 400000 sample-point 0.850
500000: bitrate 500000 sample-point 0.875
666666: bitrate 666666 sample-point 0.800
800000: bitrate 800000 sample-point 0.800
1000000: bitrate 1000000 sample-point 0.750

A drawback of the modification is that 5kbit/s is no more supported.

Setting the flexcan serial clock to 60MHz or 80MHz would produce similar
results but with losing even more bitrates at the lower end.

Changing the flexcan serial clock to 40MHz might apply for other SoCs
using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't
have such hardware to test I did not add this to the patch.

Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index dafc8806b03e..5dbb6a937732 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 		clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);
 	}
 
-	clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk);
+	clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);
 	if (clk_on_imx6ul())
 		clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);
 	else if (clk_on_imx6ull())