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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-08 21:17:14 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-08 21:17:14 +0300 |
| commit | d4da08ea37d2c84aedcf1ce9554938aabfb0714f (patch) | |
| tree | 696e848084ccb67d1867969637ec7f66483e57d5 | |
| parent | aff664cc8cbc5c28e5aa57dc4201c34497f3c871 (diff) | |
| parent | f21923f3f410f84528b5e7bdcbe4afdc6f07010c (diff) | |
| download | linux-d4da08ea37d2c84aedcf1ce9554938aabfb0714f.tar.xz | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Renesas RZ/G3E XSPI and GBETH Core DT Binding Definitions
XSPI and Gigabit Ethernet PTP reference core clock DT binding
definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and
DT source files.
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h index 1d031bf6bf03..a27132f9a6c8 100644 --- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -17,5 +17,8 @@ #define R9A09G047_CM33_CLK0 6 #define R9A09G047_CST_0_SWCLKTCK 7 #define R9A09G047_IOTOP_0_SHCLK 8 +#define R9A09G047_SPI_CLK_SPI 9 +#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |