diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2020-03-19 22:02:23 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-06 19:50:36 +0300 |
| commit | d3c32c04adfdb6c646722dc5fde1a3d88f293fd4 (patch) | |
| tree | 0325dbbef2a89bbe7a625ea10ab452f6eec5e0e6 | |
| parent | 35509737c8f958944e059d501255a0bf18361ba0 (diff) | |
| download | linux-d3c32c04adfdb6c646722dc5fde1a3d88f293fd4.tar.xz | |
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
The early-resume code shall not switch CPU to PLLX because PLLX
configuration could be unstable or PLLX should be simply disabled if
CPU enters into suspend running off some other PLL (the case if CPUFREQ
driver is active). The actual burst policy is restored by the clock
drivers.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index e7bcf7dc4675..9942265ed650 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -398,11 +398,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */ |