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authorMatt Roper <matthew.d.roper@intel.com>2023-04-21 17:50:05 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:31:42 +0300
commitd33dc1dc29cab7871f9b0adee7b94b4dc5de5cb1 (patch)
treef855506ba43f999368adb1cf11348a87c5f8f86c
parent7500477ded53343921b24e7ec5770197af710d94 (diff)
downloadlinux-d33dc1dc29cab7871f9b0adee7b94b4dc5de5cb1.tar.xz
drm/xe: Fix xe_mmio_rmw32 operation
xe_mmio_rmw32 was failing to invert the passed in mask, resulting in a register update that wasn't the expected RMW operation. Fortunately the impact of this mistake was limited, since this function isn't heavily used in Xe right now; this will mostly fix some GuC PM interrupt unmasking. v2: - Rename parameters as 'clr' and 'set' to clarify semantics. (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230421145006.10940-1-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r--drivers/gpu/drm/xe/xe_mmio.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 354be6fae0d4..be7ba2813d58 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -42,13 +42,13 @@ static inline u32 xe_mmio_read32(struct xe_gt *gt, u32 reg)
return readl(gt->mmio.regs + reg);
}
-static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 mask,
- u32 val)
+static inline u32 xe_mmio_rmw32(struct xe_gt *gt, u32 reg, u32 clr,
+ u32 set)
{
u32 old, reg_val;
old = xe_mmio_read32(gt, reg);
- reg_val = (old & mask) | val;
+ reg_val = (old & ~clr) | set;
xe_mmio_write32(gt, reg, reg_val);
return old;