diff options
| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2026-03-10 16:20:25 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2026-03-25 09:06:09 +0300 |
| commit | d19faa0dcc6abd35ed67084d8e31590a243f77c0 (patch) | |
| tree | 8b2da3d4133f121628091923c38584259ca08bc3 | |
| parent | 958adefc4c0fddee3b12269da5dd7cb49bac953f (diff) | |
| download | linux-d19faa0dcc6abd35ed67084d8e31590a243f77c0.tar.xz | |
drm/msm/mdss: Add a TODO for better managing the MDSS clock power state
There's a small window where the MDP clock could be set to a high rate
(say, from the bootloader) without a corresponding RPM(H)PD vote to
back it up. This is normally not an issue, but could be, if rmmod fails
to shut down the display driver cleanly, and the module is inserted
again, or when the providers' .sync_state has timed out.
Mark a TODO to fix it one day. Linking the relevant discussion below.
Link: https://lore.kernel.org/linux-arm-msm/d5c4eed5-bd87-4156-b178-2d78140ec8a9@oss.qualcomm.com/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/710572/
Link: https://lore.kernel.org/r/20260310-topic-mdss_power_todo-v1-1-59457b8b7486@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
| -rw-r--r-- | drivers/gpu/drm/msm/msm_mdss.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index a86776425f26..90c3fa0681a0 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -262,6 +262,14 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) icc_set_bw(msm_mdss->reg_bus_path, 0, msm_mdss->reg_bus_bw); + /* + * TODO: + * Previous users (e.g. the bootloader) may have left this clock at a high rate, which + * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a + * risk of brownout, but realistically this path is almost exclusively excercised after the + * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, + * before the RPM(H)PD sync_state is done. + */ ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); |