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authorDan Williams <dan.j.williams@intel.com>2026-01-14 21:20:34 +0300
committerDave Jiang <dave.jiang@intel.com>2026-01-23 01:06:54 +0300
commitd18f1b7beadf1af1cd334ff789ba5a07ce285bbc (patch)
treefe250b8c92e3312153e654d759d410f1b3952677
parent7ff8b1d60881c5f97b5ae426e14d2822917d3b69 (diff)
downloadlinux-d18f1b7beadf1af1cd334ff789ba5a07ce285bbc.tar.xz
PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS
One of the primary reasons for the CXL driver to exist is to perform error handling. If both PCIEAER and CXL are enabled then light up CXL error handling as well. Now that all RAS handling is moved under the CXL_RAS symbol, drop the previous PCIEAER_CXL symbol. Reviewed-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260114182055.46029-14-terry.bowman@amd.com Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
-rw-r--r--drivers/cxl/Kconfig2
-rw-r--r--drivers/pci/pcie/Kconfig9
2 files changed, 1 insertions, 10 deletions
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 217888992c88..70acddc08c39 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -235,6 +235,6 @@ config CXL_MCE
config CXL_RAS
def_bool y
- depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI
+ depends on ACPI_APEI_GHES && PCIEAER && CXL_BUS
endif
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 17919b99fa66..207c2deae35f 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -49,15 +49,6 @@ config PCIEAER_INJECT
gotten from:
https://github.com/intel/aer-inject.git
-config PCIEAER_CXL
- bool "PCI Express CXL RAS support"
- default y
- depends on PCIEAER && CXL_PCI
- help
- Enables CXL error handling.
-
- If unsure, say Y.
-
#
# PCI Express ECRC
#