diff options
| author | Zhang, Jerry <Jerry.Zhang@amd.com> | 2017-07-14 13:20:17 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-09-27 15:43:12 +0300 |
| commit | d17cec1f18b9a6a847b224a3c7e5892a8b00fd8f (patch) | |
| tree | 229eff54e00a4b80d1537f5506b173c118e07673 | |
| parent | be000b5d60d24b7613ad53e2c51e0fd06abfe897 (diff) | |
| download | linux-d17cec1f18b9a6a847b224a3c7e5892a8b00fd8f.tar.xz | |
drm/amdgpu: read reg in each iterator of psp_wait_for loop
commit 2890decfd9969cac21067ca0c734fbccaf74d634 upstream.
v2: fix the SOS loading failure for PSP v3.1
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Acked-by: Huang Rui <ray.huang@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 |
2 files changed, 1 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 4083be61b328..6417febe18b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -95,9 +95,8 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index, int i; struct amdgpu_device *adev = psp->adev; - val = RREG32(reg_index); - for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32(reg_index); if (check_changed) { if (val != reg_val) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index c98d77d0c8f8..6f80ad8f588b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -237,11 +237,9 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) /* there might be handshake issue with hardware which needs delay */ mdelay(20); -#if 0 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, true); -#endif return ret; } |