summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-11-17 17:30:06 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2016-11-17 18:11:35 +0300
commitd132d6d53e0cde244d07966832f9f7f3f41a1439 (patch)
tree63d2f18e8a0b3473fbc63fcef1f796127cd53c17
parent4881f0bad9eb56bb7257e2386ffb27ef969bb6ce (diff)
downloadlinux-d132d6d53e0cde244d07966832f9f7f3f41a1439.tar.xz
ACPI / LPSS: enable hard LLP for DMA
Right now the DMA support of hard LLP (*) is fused. Enable it via specific message sent to SoC at run time. (*) Hard LLP stands for the multi-block transfer feature of DMA controller supported by hardware. Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-rw-r--r--drivers/acpi/acpi_lpss.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 552010288135..c4712395020c 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -724,13 +724,14 @@ static int acpi_lpss_resume_early(struct device *dev)
#define LPSS_GPIODEF0_DMA1_D3 BIT(2)
#define LPSS_GPIODEF0_DMA2_D3 BIT(3)
#define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
+#define LPSS_GPIODEF0_DMA_LLP BIT(13)
static DEFINE_MUTEX(lpss_iosf_mutex);
static void lpss_iosf_enter_d3_state(void)
{
u32 value1 = 0;
- u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
+ u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
u32 value2 = LPSS_PMCSR_D3hot;
u32 mask2 = LPSS_PMCSR_Dx_MASK;
/*
@@ -774,8 +775,9 @@ exit:
static void lpss_iosf_exit_d3_state(void)
{
- u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;
- u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
+ u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
+ LPSS_GPIODEF0_DMA_LLP;
+ u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
u32 value2 = LPSS_PMCSR_D0;
u32 mask2 = LPSS_PMCSR_Dx_MASK;