diff options
| author | Stefan Riedmueller <s.riedmueller@phytec.de> | 2021-09-27 10:28:57 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2021-10-01 10:15:51 +0300 |
| commit | d1012253a2d377f389ea09a82e04b2241fb30b10 (patch) | |
| tree | f8eb8c855b665e7d124150cb784523c3171ad6d4 | |
| parent | 2f9d61869640f732599ec36b984c2b5c46067519 (diff) | |
| download | linux-d1012253a2d377f389ea09a82e04b2241fb30b10.tar.xz | |
clk: imx: imx6ul: Fix csi clk gate register
According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.
Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Tested-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx6ul.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 206e4c43f68f..520b100bff4b 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6ULL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x70, 0, &share_count_esai); hws[IMX6ULL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x70, 0, &share_count_esai); } - hws[IMX6UL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x70, 2); hws[IMX6UL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); hws[IMX6UL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); hws[IMX6UL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); @@ -391,6 +390,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6UL_CLK_PXP] = imx_clk_hw_gate2("pxp", "axi", base + 0x70, 30); /* CCGR3 */ + /* + * Although the imx6ull reference manual lists CCGR2 as the csi clk + * gate register, tests have shown that it is actually the CCGR3 + * register bit 0/1, same as for the imx6ul. + */ + hws[IMX6UL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x74, 0); hws[IMX6UL_CLK_UART5_IPG] = imx_clk_hw_gate2("uart5_ipg", "ipg", base + 0x74, 2); hws[IMX6UL_CLK_UART5_SERIAL] = imx_clk_hw_gate2("uart5_serial", "uart_podf", base + 0x74, 2); if (clk_on_imx6ul()) { |