summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChen-Yu Tsai <wens@csie.org>2017-04-05 09:37:42 +0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-05 10:01:41 +0300
commitcf719012b23278c65d0bca4975a7ea46e5bb75be (patch)
tree55ef3d9f2d96e3546304fd07619e6c1dffcb6e08
parentcdb8b80b60935515b86cfe534f69934b13937052 (diff)
downloadlinux-cf719012b23278c65d0bca4975a7ea46e5bb75be.tar.xz
clk: sunxi-ng: mult: Support PLL lock detection
Some PLL clocks are N (multiplier) type clocks, or can be simplified as such. An example of the former is the DDR1 PLL clock on the A33. An example of the latter is the CPU PLL clock on the A80, in which the P divider is only used for low frequencies that are of little use. Both clocks support PLL lock detection. The mult clock macro implies support for this, but that is not true. The field is simply discarded. This patch adds proper support for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--drivers/clk/sunxi-ng/ccu_mult.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu_mult.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 8724c01171b1..671141359895 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -137,6 +137,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
spin_unlock_irqrestore(cm->common.lock, flags);
+ ccu_helper_wait_for_lock(&cm->common, cm->lock);
+
return 0;
}
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
index 524acddfcb2e..f9c37b987d72 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.h
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -33,6 +33,7 @@ struct ccu_mult_internal {
struct ccu_mult {
u32 enable;
+ u32 lock;
struct ccu_frac_internal frac;
struct ccu_mult_internal mult;
@@ -45,6 +46,7 @@ struct ccu_mult {
_flags) \
struct ccu_mult _struct = { \
.enable = _gate, \
+ .lock = _lock, \
.mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \
.common = { \
.reg = _reg, \