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| author | Clément Léger <clement.leger@bootlin.com> | 2022-06-24 17:39:59 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-29 16:29:13 +0300 |
| commit | cda41c14ab8ae25acec3b8b956336bbb05cedc35 (patch) | |
| tree | d54c28886fb5c0e33a09c44bbfcbf04c4a0f7eef | |
| parent | c6f600923600e7af24efab1697a859d1d2389c66 (diff) | |
| download | linux-cda41c14ab8ae25acec3b8b956336bbb05cedc35.tar.xz | |
ARM: dts: r9a06g032: Describe switch
Add the description of the switch that is present on the RZ/N1 SoC. This
description includes ethernet-port descriptions for all the ports that
are present on the switch along with their connection to the MII
converter ports and to the GMAC for the CPU port.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20220624144001.95518-15-clement.leger@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 42ce02e51e8d..5b97fa85474f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -361,6 +361,57 @@ }; }; + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0>; + pcs-handle = <&mii_conv5>; + status = "disabled"; + }; + + switch_port1: port@1 { + reg = <1>; + pcs-handle = <&mii_conv4>; + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <2>; + pcs-handle = <&mii_conv3>; + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <3>; + pcs-handle = <&mii_conv2>; + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + phy-mode = "internal"; + status = "disabled"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; |