diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2026-04-11 01:50:30 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-04-13 22:41:56 +0300 |
| commit | cd84bfbba7feb4c1e72356f14de026dfda1a9e2a (patch) | |
| tree | 863c94f6b1769f6228884b0adf5663bbce20a903 | |
| parent | 0b1676eafdd1ba5a5436bdca0d2a25ce56699783 (diff) | |
| download | linux-cd84bfbba7feb4c1e72356f14de026dfda1a9e2a.tar.xz | |
drm/xe: Mark ROW_CHICKEN5 as a masked register
ROW_CHICKEN5 is a masked register (i.e., to adjust the value of any of
the lower 16 bits, the corresponding bit in the upper 16 bits must also
be set). Add the XE_REG_OPTION_MASKED to its definition; failure to do
so will cause workaround updates of this register to not apply properly.
Bspec: 56853
Fixes: 835cd6cbb0d0 ("drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10")
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-3-e206a62ee38f@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index aa267c2f6162..a4472b7acb18 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -584,7 +584,7 @@ #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) #define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32) -#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0) +#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED) #define CPSS_AWARE_DIS REG_BIT(3) #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) |