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| author | Zhen Lei <thunder.leizhen@huawei.com> | 2021-01-18 06:16:34 +0300 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2021-01-29 11:33:26 +0300 |
| commit | ccf43e02012ae5c2fc895136ab0adf98286db40f (patch) | |
| tree | 39819cd43b3359af0510b5181158055c478066b7 | |
| parent | b2bbc8687e43df456a6d194bc2c3ab9431b770cb (diff) | |
| download | linux-ccf43e02012ae5c2fc895136ab0adf98286db40f.tar.xz | |
arm64: dts: hisilicon: delete unused property smmu-cb-memtype
The "smmu-cb-memtype" is a private property developed by the Hisilicon
driver in the early stage and is not used now. So delete it.
Otherwise, below YAML check warnings are reported:
arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/hisilicon/hip07-d05.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip07.dtsi | 5 |
2 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 78050d67a786..7deca5f763d5 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -335,7 +335,6 @@ reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; dma-coherent; - smmu-cb-memtype = <0x0 0x1>; hisilicon,broken-prefetch-cmd; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index f477f442c275..2172d8071181 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1166,7 +1166,6 @@ reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; dma-coherent; - smmu-cb-memtype = <0x0 0x1>; hisilicon,broken-prefetch-cmd; status = "disabled"; }; @@ -1181,7 +1180,6 @@ #iommu-cells = <1>; dma-coherent; hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ }; p0_smmu_alg_b: iommu@8d0040000 { compatible = "arm,smmu-v3"; @@ -1194,7 +1192,6 @@ #iommu-cells = <1>; dma-coherent; hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ }; p1_smmu_alg_a: iommu@400d0040000 { compatible = "arm,smmu-v3"; @@ -1207,7 +1204,6 @@ #iommu-cells = <1>; dma-coherent; hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ }; p1_smmu_alg_b: iommu@408d0040000 { compatible = "arm,smmu-v3"; @@ -1220,7 +1216,6 @@ #iommu-cells = <1>; dma-coherent; hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ }; soc { |