diff options
| author | Michael Riesch <michael.riesch@collabora.com> | 2026-05-23 00:23:11 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-05-29 14:42:02 +0300 |
| commit | c7126247fb797127ced68691583932d0a05bbd68 (patch) | |
| tree | 93ea00929927b11bebbb4091f3dd1b10b6a854f9 | |
| parent | d8d7e7549312c50fa5dcd69a6dc6f0035e770c09 (diff) | |
| download | linux-c7126247fb797127ced68691583932d0a05bbd68.tar.xz | |
arm64: dts: rockchip: add vicap node to rk3588
Add the device tree node for the RK3588 Video Capture (VICAP) unit.
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
[converted reg values in vicap ports to hexadecimal, to have them align
with the port@X values, and be less confusing]
Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-5-d1d1f5265c56@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4aff2701febf..a22da6671da3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1474,6 +1474,89 @@ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + vicap: video-capture@fdce0000 { + compatible = "rockchip,rk3588-vicap"; + reg = <0x0 0xfdce0000 0x0 0x800>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>, + <&cru ICLK_CSIHOST1>; + clock-names = "aclk", "hclk", "dclk", "iclk", "iclk1"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>, + <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, + <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, + <&cru SRST_CSIHOST5_VICAP>; + reset-names = "arst", "hrst", "drst", "irst0", "irst1", + "irst2", "irst3", "irst4", "irst5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0x0>; + }; + + vicap_mipi0: port@1 { + reg = <0x1>; + }; + + vicap_mipi1: port@2 { + reg = <0x2>; + }; + + vicap_mipi2: port@3 { + reg = <0x3>; + + vicap_mipi2_input: endpoint { + remote-endpoint = <&csi2_output>; + }; + }; + + vicap_mipi3: port@4 { + reg = <0x4>; + }; + + vicap_mipi4: port@5 { + reg = <0x5>; + + vicap_mipi4_input: endpoint { + remote-endpoint = <&csi4_output>; + }; + }; + + vicap_mipi5: port@6 { + reg = <0x6>; + }; + + vicap_toisp0: port@10 { + reg = <0x10>; + }; + + vicap_toisp1: port@11 { + reg = <0x11>; + }; + }; + }; + + vicap_mmu: iommu@fdce0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1496,6 +1579,10 @@ csi2_out: port@1 { reg = <1>; + + csi2_output: endpoint { + remote-endpoint = <&vicap_mipi2_input>; + }; }; }; }; @@ -1522,6 +1609,10 @@ csi4_out: port@1 { reg = <1>; + + csi4_output: endpoint { + remote-endpoint = <&vicap_mipi4_input>; + }; }; }; }; |