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| author | Richard Zhu <hongxing.zhu@nxp.com> | 2025-10-15 06:04:25 +0300 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2026-01-21 10:31:08 +0300 |
| commit | c577ce2881f9c76892de5ffc1a122e3ef427ecee (patch) | |
| tree | bddc8679c044a1487fc405e3e5f0a798e57c6278 | |
| parent | d8574ce57d760a958623c8f6bc3c55b5187a7bd7 (diff) | |
| download | linux-c577ce2881f9c76892de5ffc1a122e3ef427ecee.tar.xz | |
PCI: dwc: Invoke post_init in dw_pcie_resume_noirq()
In some SoCs like i.MX95, CLKREQ# is pulled low by the controller driver
before link up. After link up, if the 'supports-clkreq' property is
specified in DT, the driver will release CLKREQ# so that it can go high and
the endpoint can pull it low whenever required i.e., during exit from L1
Substates.
Hence, at the end of dw_pcie_resume_noirq(), invoke the '.post_init()'
callback if exists to perform the above mentioned action.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251015030428.2980427-9-hongxing.zhu@nxp.com
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-host.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 372207c33a85..9ea5335e5d8c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1231,6 +1231,9 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci) if (ret) return ret; + if (pci->pp.ops->post_init) + pci->pp.ops->post_init(&pci->pp); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); |