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| author | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2025-06-10 15:09:35 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2025-06-12 17:50:00 +0300 |
| commit | c0c7fa4e7a512006710c8e4d6b6f7b40c9f786cd (patch) | |
| tree | f3a60b811ee196da3d8c669409526a28b86b9d99 | |
| parent | 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff) | |
| download | linux-c0c7fa4e7a512006710c8e4d6b6f7b40c9f786cd.tar.xz | |
docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst
Fix trivial ICC_SRE_EL2 register spelling typo in booting.rst.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Will Deacon <will@kernel.org>
CC: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250610120935.852034-1-lpieralisi@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/arch/arm64/booting.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index dee7b6de864f..ee9b790c0d72 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met: - If the kernel is entered at EL1: - - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 + - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. - The DT or ACPI tables must describe a GICv3 interrupt controller. |