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authorVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>2024-09-24 13:05:57 +0300
committerBjorn Andersson <andersson@kernel.org>2024-10-06 05:05:40 +0300
commitc014190967dbc731b138e99800debabebf06058f (patch)
treeb76cb4901af9b938636635f33977752d6fd9e9f9
parent30326d120ac855490b0580eaad290bc7eff2d9c1 (diff)
downloadlinux-c014190967dbc731b138e99800debabebf06058f.tar.xz
arm64: dts: qcom: sm8450: don't disable dispcc by default
Enable display clock controller for all Qualcomm SM8450 powered boards by default. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8450.dtsi1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9bafb3b350ff..da378c2ed482 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3435,7 +3435,6 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- status = "disabled";
};
pdc: interrupt-controller@b220000 {