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| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2025-10-15 13:27:31 +0300 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-10-19 10:13:33 +0300 |
| commit | bc427cd81b2a42be41be87c976cdc847f44353bf (patch) | |
| tree | 9155a03b20d55021a3e6a89303c562e446016327 | |
| parent | dfbf19c47a01eda5df4d476d64a273e1188ea5a1 (diff) | |
| download | linux-bc427cd81b2a42be41be87c976cdc847f44353bf.tar.xz | |
dt-bindings: PCI: qcom,pcie-sm8550: Add Kaanapali compatible
On the Qualcomm Kaanapali platform the PCIe host is compatible with the
DWC controller present on the SM8550 platform.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251015-kaanapali-pcie-upstream-v2-1-84fa7ea638a1@oss.qualcomm.com
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 38b561e23c1f..8f02a2fa6d6e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,kaanapali-pcie - qcom,sar2130p-pcie - qcom,pcie-sm8650 - qcom,pcie-sm8750 |