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| author | Sameer Pujar <spujar@nvidia.com> | 2019-01-14 21:21:10 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2019-01-14 21:52:27 +0300 |
| commit | b59c8e7a73160b11f99b9008a5f215dd54b9d581 (patch) | |
| tree | 16864b2d1fa959a400427c3ffc5e83a8aed64c6a | |
| parent | 5dd3d271320d888bb708ca6252b8a9e416a7fe64 (diff) | |
| download | linux-b59c8e7a73160b11f99b9008a5f215dd54b9d581.tar.xz | |
ALSA: hda: add register offset for stripe control
bits 16:17 in SD_CTL register refer to stripe control. Added an
offset register(AZX_REG_SD_CTL_3B) to have exclusive read/write
of corresponding register byte. This helps to avoid unnecessary
32-bit read/write of SD_CTL whenever only stripe or other bits of
corresponding byte need to be updated. Also HD audio spec defines
SD_CTL as 3 byte register.
SD_CTL_STRIPE_MASK(0x3) can be used for stripe control programming
and when updating AZX_REG_SD_CTL_3B.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
| -rw-r--r-- | include/sound/hda_register.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 2ab39fb52d7a..0fd39295b426 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -79,6 +79,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; /* stream register offsets from stream base */ #define AZX_REG_SD_CTL 0x00 +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ #define AZX_REG_SD_STS 0x03 #define AZX_REG_SD_LPIB 0x04 #define AZX_REG_SD_CBL 0x08 @@ -165,6 +166,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define SD_INT_COMPLETE 0x04 /* completion interrupt */ #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ SD_INT_COMPLETE) +#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ /* SD_STS */ #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ |