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authorCyril Chemparathy <cyril@ti.com>2010-10-21 01:49:56 +0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-12-10 18:33:49 +0300
commitb1d05be61f5d29118c2934e684628a5034186825 (patch)
tree8e352e171eb4a0f14538317f3917a5fabf746341
parent6d1c57c84cc474a0fa63aadaa260b13dc5c7d68b (diff)
downloadlinux-b1d05be61f5d29118c2934e684628a5034186825.tar.xz
davinci: use divide ratio limits from pll_data
This patch modifies the sysclk rate setting code to use the divider mask specified in pll_data. Without this, devices with different divider ranges (e.g. tnetv107x) fail. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
-rw-r--r--arch/arm/mach-davinci/clock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 01ba080433db..e4e3af179f02 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
ratio--;
}
- if (ratio > PLLDIV_RATIO_MASK)
+ if (ratio > pll->div_ratio_mask)
return -EINVAL;
do {
@@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
} while (v & PLLSTAT_GOSTAT);
v = __raw_readl(pll->base + clk->div_reg);
- v &= ~PLLDIV_RATIO_MASK;
+ v &= ~pll->div_ratio_mask;
v |= ratio | PLLDIV_EN;
__raw_writel(v, pll->base + clk->div_reg);