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| author | Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> | 2026-05-18 09:35:47 +0300 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-05 20:17:27 +0300 |
| commit | afb61965f3dab1505574e9a9b212bb2f367ec5dd (patch) | |
| tree | 57309ba0334dfdf6cdfc85d017a396528fc88374 | |
| parent | 95f5bc1632ab8f243e517357b5da0dd28d1c6c92 (diff) | |
| download | linux-afb61965f3dab1505574e9a9b212bb2f367ec5dd.tar.xz | |
arm64: dts: s32g: add PIT support for s32g2 and s32g3
Add PIT0 and PIT1 for S32G2 and S32G3 SoCs
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 |
2 files changed, 38 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 51d00dac12de..f508b776b4dd 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -417,6 +417,15 @@ clock-names = "dmamux0", "dmamux1"; }; + pit0: timer@40188000 { + compatible = "nxp,s32g2-pit"; + reg = <0x40188000 0x3000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can0: can@401b4000 { compatible = "nxp,s32g2-flexcan"; reg = <0x401b4000 0xa000>; @@ -622,6 +631,15 @@ clock-names = "dmamux0", "dmamux1"; }; + pit1: timer@40288000 { + compatible = "nxp,s32g2-pit"; + reg = <0x40288000 0x3000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can2: can@402a8000 { compatible = "nxp,s32g2-flexcan"; reg = <0x402a8000 0xa000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index e314f3c7d61d..efe5398e1240 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> * Ciprian Costea <ciprianmarian.costea@nxp.com> @@ -475,6 +475,15 @@ clock-names = "dmamux0", "dmamux1"; }; + pit0: pit@40188000 { + compatible = "nxp,s32g3-pit", "nxp,s32g2-pit"; + reg = <0x40188000 0x3000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can0: can@401b4000 { compatible = "nxp,s32g3-flexcan", "nxp,s32g2-flexcan"; @@ -693,6 +702,15 @@ clock-names = "dmamux0", "dmamux1"; }; + pit1: pit@40288000 { + compatible = "nxp,s32g3-pit", "nxp,s32g2-pit"; + reg = <0x40288000 0x3000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 61>; + clock-names = "pit"; + status = "disabled"; + }; + can2: can@402a8000 { compatible = "nxp,s32g3-flexcan", "nxp,s32g2-flexcan"; |